1. Field of the Invention
The present invention relates to a sensing amplifier, a memory device and a related enhancement method for boosting the sensing amplifier, and more particularly, to a sensing amplifier and related apparatus and enhancement method for boosting the sensing amplifier by making use of a P-sensing enhancement circuit to boost a voltage level of a bit line or a complementary bit line to a reference voltage when the bit line as well as the complementary bit line are isolated from the sensing amplifier.
2. Description of the Prior Art
A semiconductor memory can be divided into two categories: a volatile memory, e.g. a dynamic random access memory (DRAM), and a non-volatile memory. The difference between these categories is whether the stored data can be reserved for a long time when external electric power is turned off. The data stored in the DRAM will disappear but the data stored in the non-volatile memory will be preserved.
Please refer to FIG. 1 (including 1A and 1B). 1A is a simplified diagram of a memory device 100 according to the prior art, and 1B is a diagram showing a problem resulted in the sensing amplifier 130 of the memory device 100. As shown in 1A, the memory device 100 includes at least one memory array 110 and 120, a sensing amplifier 130, a first switch circuit 140, a second switch circuit 150, and a boosting circuit 190. The boosting circuit 190 is disposed between the sensing amplifier 130 and the first switch circuit 140 for boosting a sensing line/complementary sensing line SA/bSA during a boosting stage. The first switch circuit 140 is disposed between the sensing amplifier 130 and the memory array 110 for determining whether to isolate a bit line/complementary bit line BL/bBL from a sensing line/complementary sensing line SA/bSA. The second switch circuit 150 is disposed between the sensing amplifier 130 (via the boosting circuit 190) and the memory array 120 for determining whether to isolate another bit line/complementary bit line from the sensing line/complementary sensing line SA/bSA. Be noted that a parasitic capacitor C2 located on the bit line/complementary bit line BL/bBL is usually greater than a parasitic capacitor C1 located on the sensing line/complementary sensing line SA/bSA.
In 1B of FIG. 1, it shows a traditional waveform of the boosted sensing line/complementary sensing line SA/bSA together with the bit line/complementary bit line BL/bBL. At first, the second switch circuit 150 is turned off and the first switch circuit 140 is turned on. At this time, the bit line BL and the complementary bit line bBL start to develop, which is also labeled as a duration T1. And then the first switch circuit 140 is turned off, so that the bit line BL is isolated from the sensing line SA and the complementary bit line bBL is isolated from the complementary sensing line bSA, which is also labeled as a duration T2. During the duration T2 (which is also called as the boosting stage), the sensing line SA and the complementary sensing line bSA are boosted by the boosting circuit 190. Afterwards, the complementary sensing line bSA is pulled up from ½ VbLH to VbLH while the sensing line SA is pulled down from ½ VbLH to 0 during a duration T3. After that, the first switch circuit 140 is turned on again, so that the bit line BL is re-connected to the sensing line SA and the complementary bit line bBL is re-connected to the complementary sensing line bSA, which is also labeled as a duration T4. During the duration T4, the sensing line/complementary sensing line SA/bSA and the bit line/complementary bit line BL/bBL will have charge sharing. As can be seen from 1B of FIG. 1, because the parasitic capacitor C2 located on the bit line/complementary bit line BL/bBL is much bigger than the parasitic capacitor C1 located on the sensing line/complementary sensing line SA/bSA, a great glitch may appear in the bit line/complementary bit line BL/bBL. This may cause false sensing and may increase the recovery time of the bit line/complementary bit line BL/bBL.
Hence, how to overcome such problem, resulted from the glitch appeared in the bit line/complementary bit line BL/bBL in the sensing amplifier of the memory device, has become an important topic of the field.